1. Field of the Invention
This invention relates to an apparatus and a process for testing semiconductor device die before the die are assembled into a package.
2. Related Art
Semiconductor die are conventionally made in large area wafers such that hundreds or thousands of identical individual die are simultaneously made. Such die can be diodes, transistors, MOSFETs, IGBTs and the like. After the wafer (containing the unseparated die) is completed, it is placed in an apparatus which probes and tests the die for certain characteristics (called "wafer probe" or "probe" test). Those die which fail the probe test for any reason are normally marked with an ink dot or the like.
The die are then separated from one another within the wafer as by a singulating operation (such as sawing). Usually the separated (or singulated) die of the wafer are held together by an adhesive backing. The separated wafer is then placed in an assembly operation in which only unmarked "good" die are picked up and then deposited into a package (or stored in a tape and reel assembly) which will have one or more of the die.
Frequently die which pass the probe test in the wafer are damaged during the die separation process. Furthermore, the wafer probe test is not a full and accurate test of the acceptability of the die for their intended purpose because the presence of the surrounding die reduces testing accuracy and militates against running certain tests, such as high current tests.
Test measurements at wafer probe must be conducted below about 7 amperes in order to prevent device damage. At wafer probe testing, current is injected through one or more fine probe needles (which measure a few thousands of an inch in diameter). If a probe needle is misaligned, currents above about seven amperes cause localized damage to the semiconductor die which may manifest in latent reliability defects.
With wafer probe test, electrical connection to one side of the wafer (for example, the drain metal) is made by way of a mounting vacuum chunk. If good intimate electrical contact with the drain metal of the wafer is not obtained (due to small particles or a non-planar wafer profile), then probe current may flow laterally through the silicon substrate or the back metalization of the wafer. Such current flow increases the measured series resistance of the die being probed, thereby causing an inaccurate Rdson and Vsd reading.
Although drain and gate leakage tests (such as Idss and Igss) may be performed at wafer probe on certain types of die (for example, FET die), the measured values may not reflect the leakage values which would be found in a final semiconductor package because the leakage values easily change after the wafers have gone through the wafer probe test and the die are separated.
After wafer probe, wafers are handled extensively and exposed to environmental micro-contamination and moisture. Further, the wafers are singulated (sawed) in an aqueous system and then dried. The sawing process can cause chip-outs along the cut that can affect the electrical field termination around the periphery of the die, thereby causing leakages to increase (for example, Idss leakage). Furthermore, the handling and exposure can create surface leakage paths across the die.
Wafer probe testing has not previously been used to perform avalanche testing of die due to current constraints, lead lengths, equipment maintenance and difficulty in making contact with the die. Thus, it has not been possible to test the reverse breakdown of a die at wafer probe.
Although temperature testing at high temperatures has been performed during wafer probe, temperature testing at low temperatures is not performed. This is so because multiple temperature testing at wafer probe would require repeated contacting of the surface of the die which would likely result in damage to the metalization of the die.
Wafer probe testing is unsuited for dynamic switch testing of transistors (for example, IGBTs) and UIS testing due to the current constraints and interference between adjacent die in the wafer.
Due to the testing limitations and inaccuracies discussed above during wafer probe, some die pass wafer probe and are treated as "good die" when in fact they are defective. Conversely, some die fail wafer probe test and are treated as bad die when in fact a more accurate test would have found them to be "good die".
As a result, good die may be discarded and improperly unmarked "good" die are frequently assembled in package form and defects discovered only when the packaged device is fully tested. This process is, of course, wasteful since good die are discarded and the defective die are discovered only after the costly packaging operation is completed.
U.S. Pat. No. 5,475,317 is directed to a singulated semiconductor die tester and method for performing burn-in electrical tests. A die carrier 4 is employed which includes a plurality of elastomeric probes 4a in alignment which bond pads 2a of a die 2. Allegedly, the elastomeric probes 4a have been designed to continuously and repetitively establish electrical continuity with bond pads 2a of different die 2. An alignment template 6 is disposed proximate to the die 2 to ensure that the die is properly aligned with the carrier 4. The '317 patent discloses that burn-in testing may be utilized with the die tester by inserting it and the die into heating and/or cooling chambers to achieve testing at minus 55.degree. C. to 125.degree. C., for example. A TEC cooler 30 (FIG. 5) is also disclosed as being effective in achieving temperature testing of the die 2.
U.S. Pat. No. 5,589,781 discloses a die carrier apparatus 700 which includes a carrier block 702 for receiving a chip alignment plate 770 in which a semiconductor chip under test is disposed. A probe card 800 includes a plurality of needles 310 for contacting the semiconductor chip when the probe card 800 is positioned above the alignment plate 770. Probe traces 802 provide electrical connection between the needles 310 and the periphery of the probe card 800.
U.S. Pat. No. 5,629,631 is directed to an interface card and probe card for testing unpackaged semiconductor die. The patent discloses a probe card assembly 20 having an interface card 22, a probe card 24, and a carousel 26 disposed between the interface card 22 and the probe card 24. The probe card 24 is not fixed to the carousel 26 and may be precisely stepped such that it aligns with a semiconductor wafer to be tested. The interface card 22 is formed from a ceramic body which include contact pads 56 on a top layer, an internal layer having wiring metalization 58 and a bottom layer having contact pads 60 making contact with a connector. The contact pads 56 on the top layer are offset from the contact pads 60 on the bottom layer such that they are closer to the periphery of the interface card 22. The wiring metalization 58 connects the contact pads 56 with the contact pads 60.
The '631 patent also discloses a guard circuit for reducing current leakage in the probe card 24. The guard circuit includes guard line metalization 82 on either side of contact pads 74 and 76 of a top layer 68 and guard line metalization 84 on either side of signal lines 80 on a second layer 70. A third layer 72 includes metal pads 86 directly below signal lines 80 and line metalization 84. A central opening is included in the probe card 24 for receiving standard semiconductor wafer probes 78 for contacting the semiconductor wafer under test.
The above listed patents do not adequately address the problems in the art. Indeed, it would be desirable to increase the accuracy of tests for "known-good-die" in a wafer, and, in particular, it would be desirable to test the singulated die before the die are mounted in packages or housings.